Generally, a liquid crystal display includes an upper substrate, a lower substrate and a liquid crystal layer disposed between the upper substrate and the lower substrate. The liquid crystal display includes multiple pixel units. Each pixel unit includes a pixel electrode and a common electrode, and a liquid crystal capacitance may be formed between the pixel electrode and the common electrode. The orientations of liquid crystal molecules rotated or twisted may vary (be controlled) by the pixel voltage applied between the pixel electrode and the common electrode. Therefore, the transmittance of light passing through the liquid crystal layer may be controlled, and the brightness of each pixel unit of the liquid crystal display may be controlled.
FIG. 1 is an equivalent circuit diagram illustrating a pixel unit of a conventional liquid crystal display 100. The liquid crystal display 100 includes a gate driver 111, a source driver 112, multiple gate lines 121 and multiple data lines 122. The gate lines 121 are separated from the data lines 122. The intersection of the gate lines 121 and data lines 122 defines multiple pixel units 130. Each pixel unit 130 includes a liquid crystal capacitor 127 formed by a pixel electrode 124 and a common electrode 125, and a storage capacitor 128 formed by the pixel electrode 124 and a storage capacitance line. A thin-film transistor 123 includes a gate 1231 connected to the gate driver 111 via the gate line 121, a source 1232 connected to the source driver 112 via the data line 122, and a drain 1233 connected to the pixel electrode 124.
When the liquid crystal display 100 is in an operation state, two different voltages are applied to the pixel electrode 124 and the common electrode 125 respectively to form an electric field for controlling the liquid crystal layer, and the orientation of liquid crystal molecules may vary by the applied pixel voltage. Therefore, the transmittance of light passing through the liquid crystal layer may be controlled, and the brightness of each pixel unit of the liquid crystal display may be controlled. In order to get a better transmittance and brightness of light, a certain pixel voltage needs to be maintained, i.e., a certain potential difference needs to be maintained between the pixel electrode 124 and the common electrode 125.
FIG. 2 is a schematic diagram of an operation waveform of a pixel unit in the prior art. As shown in FIG. 1 and FIG. 2, in a driving process, the gate driver 111 may output a gate scanning signal V1g to the gate 1231 of the thin-film transistor 123 via the gate line 121, and output a common voltage signal V1com to the common electrode 125; the source driver 112 may output a source signal V1s to the source 1232 of the thin-film transistor 123 via the data line 122. As shown in FIG. 2, within each frame cycle, the common electrode 125 may maintain a constant potential V1com. When the gate scanning signal V1g is at a rising edge, the thin-film transistor 123 may be switched on; when the gate scanning signal V1g is at a falling edge, the thin-film transistor 123 may be switched off. The source 1232 may maintain a constant potential higher than the potential of the common electrode 125 in a period which is from a time before the thin-film transistor 123 is switched on to a time after the thin-film transistor 123 is switched off. When the thin-film transistor 123 is switched on, the potential of the drain 1233 may begin to increase until it reaches the same potential as the source 1232. Thus, a voltage may be maintained between the common electrode 125 and the pixel electrode 124 connected to the thin-film transistor 123.
However, a parasitic capacitance exists between the gate and the drain of a thin-film transistor. Because of the coupling of the parasitic capacitance, a feed through effect exists in the thin-film transistor 123. That is, as soon as the gate 1231 is cut off, the potential of the drain 1233 may abruptly decrease comparing with the potential of the source 1232, where the decreased potential difference refers to as a feed through voltage. The potential change of the drain 1233 is shown in the waveform V1d in FIG. 2. Due to the feed through voltage generated from the feed through effect, the potential of the drain 1233 may decrease, i.e., the potential of the pixel electrode 124 may decrease, and therefore the voltage between the pixel electrode 124 and the common electrode 125 may become lower than a predetermined pixel voltage, which may affect the orientations of liquid crystal molecules and the transmittance and brightness of light of the liquid crystal display 100. Therefore, due to the feed through effect, after the thin-film transistor 123 is switched off, the liquid crystal display 100 may be provided with different transmittances and brightness of light, i.e., a flicker may occur, and thereby the image quality of the liquid crystal display 100 may be affected.
Therefore, as shown in a top view of the pixel unit in the prior art shown in FIG. 3a, the horizontal gate scanning lines 121 intersects with the vertical data lines 122 to form pixel units. The gate scanning lines and the data lines are insulated from each other by an insulating layer. Each pixel unit includes a pixel electrode 124, a storage capacitance line 22 paralleling the gate scanning line 121, and a parasitic capacitance between the gate scanning line 121 and the drain 1233 (i.e., a gate drain parasitic capacitance Cgd), which have all been designed carefully. The parasitic capacitance may be designed as small as possible to obtain a small feed through voltage. That is, the overlapped area of the gate and the drain, excepting the area for driving the thin-film transistor where the gate and the drain are overlapped, is as small as possible, and therefore the liquid crystal display may have a good performance.
FIG. 3b is a sectional view taken along A-A′ of FIG. 3a, showing the top view of the pixel unit in the prior art. As shown in FIG. 3b, the gate scanning line 121 is disposed on the substrate 28. A gate insulating layer 25 is disposed on the gate scanning line 121. The drain 1233 is disposed on the gate insulating layer 25. A passivation layer 26 is disposed on the gate insulating layer 25 and the drain 1233. The pixel electrode 124 is disposed on the passivation layer 26. A gap 23 exists between the drain 1233 and the gate scanning line 121 (i.e., the non-overlapped area of the gate and the drain). In order to avoid the possible light leak from the gap 23, a black matrix 29 of a color filter disposed above the gate line 121 may be adopted to shield the light leak. The width of the black matrix 29 may be greater due to the gap 23. Therefore, the aperture ratio of the entire pixel may be affected. In an energy-shortage era, the increasing of the aperture ratio of the pixel may lead to the reduction in cost and power consumption.